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FAN8035
6-CH Motor Driver
Features
* * * * * * * * 5-CH Balanced Transformerless (BTL) Driver 1-CH (Forward Reverse) Control DC Motor Driver Operating Supply Voltage (4.5 V ~ 13.2 V) Built in Thermal Shut Down Circuit (TSD) Built in Channel Mute Circuit Built in Power Save Mode Circuit Built in TSD Monitor Circuit Built in 2-OP AMPs
Description
The FAN8035 is a monolithic integrated circuit suitable for a 6-CH motor driver which drives the tracking actuator, focus actuator, sled motor, spindle motor, and tray motor of the CDP/CAR-CD/DVDP systems.
48-QFPH-1414
Typical Application
* * * * Compact Disk Player Video Compact Disk Player Car Compact Disk Player Digital Video Disk Player
Ordering Information
Device FAN8035 FAN8035L FAN8035_NL
note
Package 48-QFPH-1414 48-QFPH-1414 48-QFPH-1414
Operating Temperature -35C ~ +85C -35C ~ +85C -35C ~ +85C
Note: NL : Lead free Type
Rev. 1.0.4
(c)2003 Fairchild Semiconductor Corporation
FAN8035
Pin Assignments
OPOUT1
OPOUT2
OPIN1-
OPIN1+
OPIN2+
OPIN2-
PVCC1 38
SVCC
VREF
FIN (GND)
48 IN1- 1 2
47
46
45
44
43
42
41
40
39
37 36 35 34 33 32 31 DO1-
DO1+
IN1+
PS
OUT1
DO2+ DO2- PGND1
IN2+ 3 IN2- 4 OUT2 5 IN3+ 6
DO3+ DO3- FIN (GND)
FIN (GND)
FAN8035
7 8 9 30 29 28 27
IN3- OUT3 IN4+
DO4+ DO4- DO5+ DO5-
IN4- 10 OUT4 11 IN5+ 12 13 IN5- 14 OUT5 15 CTL 16 FWD 17 REV 18 SGND (GND) FIN 19 MUTE12 20 MUTE34 21 MUTE5 22 TSD-M 23 PVCC2 24 DO6-
26 PGND2 25 DO6+
2
FAN8035
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name IN1OUT1 IN2+ IN2OUT2 IN3+ IN3OUT3 IN4+ IN4OUT4 IN5+ IN5OUT5 CTL FWD REV SGND MUTE12 MUTE34 MUTE5 TSD-M PVCC2 DO6DO6+ PGND2 DO5DO5+ DO4DO4+ DO3DO3+ I/O I O I I O I I O I I O I I O I I I I I I O O O O O O O O O Pin Function Description CH1 OP-AMP Input (-) CH1 OP-AMP Output CH2 OP-AMP Input (+) CH2 OP-AMP Input (-) CH2 OP-AMP Output CH3 OP-AMP Input (+) CH3 OP-AMP Input (-) CH3 OP-AMP Output CH4 OP-AMP Input (+) CH4 OP-AMP Input (-) CH4 OP-AMP Output CH5 OP-AMP Input (+) CH5 OP-AMP Input (-) CH5 OP-AMP Output CH6 Motor Speed Control CH6 Forward Input CH6 Reverse Input Signal Ground Mute For CH1,2 Mute For CH3,4 Mute For CH5 TSD Monitor Power Supply Voltage 2 (For CH5, CH6) CH6 Drive Ouptut (-) CH6 Drive Output (+) Power Ground 2 (FOR CH5, CH6) CH5 Drive Ouptut (-) CH5 Drive Output (+) CH4 Drive Ouptut (-) CH4 Drive Output (+) CH3 Drive Ouptut (-) CH3 Drive Output (+)
3
FAN8035
Pin Definitions (Continued)
Pin Number 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name PGND1 DO2DO2+ DO1DO1+ PVCC1 PS OPOUT2 OPIN2OPIN2+ VREF SVCC OPOUT1 OPIN1OPIN1+ IN1+ I/O O O O O I O I I I O I I I Pin Function Description Power Ground 1 (FOR CH1, CH2, CH3, CH4) CH2 Drive Ouptut (-) CH2 Drive Output (+) CH1 Drive Ouptut (-) CH1 Drive Output (+) Power Supply Voltage 1 (FOR CH1, CH2, CH3, CH4) Power Save Normal OP-AMP2 output Normal OP-AMP2 Input (-) Normal OP-AMP2 Input (+) Bias Voltage Input Signal & OPAMPs Supply Voltage Normal OP-AMP1 Output Normal OP-AMP1 Input (-) Normal OP-AMP1 Input (+) CH1 OP-AMP Intput (+)
4
FAN8035
Internal Block Diagram
IN1+ 48 OPIN1+ OPIN1- OPOUT1 SVCC 47 46 - + 45 44 VREF 43 -+
-
FIN (GND)
OPIN2+ OPIN2- OPOUT2 42 41 - + 40
PS 39
PVCC1 38
DO1+ 37
IN1-
1
POWER SAVE
36
DO1-
OUT1
2
+
+ -
35
DO2+
IN2+
3
+ - -
34 DO2-
+
IN2-
4
+ -
33
PGND1
OUT2
5
- +
+ -
32
DO3+
IN3+
6
+ -
31
+ - -
DO3- FIN (GND)
FIN (GND) T.S.D IN3- 7 + -
+
30
+ -
DO4+
OUT3
8
- +
29
DO4-
IN4+
9
28 + -
+ -
DO5+
IN4-
10 + -
MUTE12
27 D D 25
MUTE34 MUTE5 TSD-M
DO5-
OUT4
11
S W
M S C
26
PGND2
IN5+
12
DO6+
13 IN5- Note.
14 OUT5
15 CTL
16 FWD
17 REV
18 SGND
19
20
21
22
23
24
(GND) MUTE12 MUTE34 MUTE5 TSD-M PVCC2 DO6- FIN
Detailed circuit of the output power amp 40K 10K From input opamp 10K Pref 10K - + 40K 40K + - 10K 40K Pref1 is almost PVCC1 / 2 Pref2 is almost PVCC2 / 2 DODO+
Vref
5
FAN8035
Equivalent Circuits
Description Pin No Internal Circuit
VCC
VCC
2K 2K
1 7 13 4 10 46
BTL INPUT & OP-AMP1 INPUT
1,4,7,10,13,46 3,6,9,12,47,48
3 9 47
6 12 48
VCC
5K 5K
VCC
OP-AMP2 INPUT
41,42
42 41
VCC
1K 5K
VCC
VREF
43
43
1K
VCC
VCC
BTL OP-AMP OUT & OP-AMP1 OUT
2,5,8,11,14,45
2 8 14
5 11 45
6
FAN8035
Equivalent Circuits (Continued)
Description Pin No Internal Circuit
VCC VCC
OP-AMP2 OUT
40
40
0.05k 0.05k
VCC
20K
MUTE12,34,5
19,20,21
19 20 21
50K 50K
VCC
CTL
15
15
1K
39K
TSD-M
22
22
20k
7
FAN8035
Equivalent Circuits (Continued)
Description Pin No Internal Circuit
VCC
100k
PS
39
39
50K 50K
VCC
30K
FWD,REV
16,17
17 16
30K 30K
30K
freewheeling diode vcc VCC
BTL CH1,2,3,4,5 OUTPUT
27 28 30 32 35 37
VCC
27,28,29,30,31 32,34,35,36,37
29 31 40 34 36
40K 7K
parastic diode
freewheeling diode VCC vcc
VCC
BTL CH6 OUTPUT
24,25
24
25
60K 7K
parastic diode
8
FAN8035
Absolute Maximum Ratings ( Ta=25C)
Parameter Maximum Supply Voltage Power Dissipation Operating Temperature Storge Temperature Maximum Output Current Symbol SVCCMAX PVCC1 PVCC2 PD TOPR TSTG IOMAX Value 18 18 18 3
note
Unit V V V W C C A
-35 ~ +85 -55 ~ +150 1
Notes: 1. When mounted on 70mm x 70mm x 1.6mm PCB. 2. Power dissipation is derated with the rate of -24mW/C for TA25C. 3. Do not exceed PD and SOA.
Pd (mW) 3,000 2,000
1,000 0 0 25 50 75 100 125 150 175 Ambient temperature, Ta [C]
Recommended Operating Conditions ( Ta=25C)
Parameter Operating Supply Voltage Symbol SVCC PVCC1 PVCC2 Min. 4.5 4.5 4.5 Typ. Max. 13.2 13.2 13.2 Unit V V V
9
FAN8035
Electrical Characteristics
(SVCC = 5V, PVCC1 = 5V, PVCC2 = 12V, TA = 25C, unless otherwise specified) Parameter Quiescent Circuit Current Power Save On Current Power Save On Voltage Power Save Off Voltage Mute12 On Voltage Mute12 Off Voltage Mute34 On Voltage Mute34 Off Voltage Mute5 On Voltage Mute5 Off Voltage BTL DRIVER CIRCUIT Output Offset Voltage Maximum Output Voltage1 Maximum Output Voltage2 Closed-loop Voltage Gain Ripple Rejection Ratio Slew Rate
note2 note2
Symbol ICC IPS
note1
Conditions Under no-load Under no-load Pin39 = Variation Pin39 = Variation Pin19 = Variation Pin19 = Variation Pin20 = Variation Pin20 = Variation Pin21 = Variation Pin21 = Variation VIN = 2.5V RL = 10, CH1,2 RL = 18, CH3,4,5 VIN = 0.1Vrms VIN = 0.1Vrms, f = 120Hz Square, Vout = 4Vp-p RL = 50 RL = 50 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p
Min. 2 2 2 2 -100 2.5 8.5 16.8 1 -10 4.4 1 1 -0.3 -
Typ. 30 3.5 10.0 18 60 2 4.7 0.2 2 2 80 65 80 1.5
Max. 1 0.5 0.5 0.5 0.5 +100 19.2 +10 400 0.5 4.0 -
Unit mA mA V V V V V V V V mV V V dB dB V/s mV nA V V mA mA V dB dB dB V/s
VPSON VPSOFF VMON12 VMOFF12 VMON34 VMOFF34 VMON5 VMOFF5 VOO VOM1 VOM2 AVF RR SR VOF1 IB1 VOH1 VOL1 ISINK1 ISOU1 Vicm1 GVO1 RR1 CMRR1 SR1
INPUT OPAMP CIRCUIT Input Offset Voltage1 Input Bias Current1 High Level Output Voltage1 Low Level Output Voltage1 Output Sink Current1 Output Source Current1 Common Mode Input Range1note2 Open Loop Voltage Gain1note2 Ripple Rejection Ratio1note2 Common Mode Rejection Ratio1note2 Slew Rate1note2
Note : 1. When the voltage at pin39 goes below 0.5V, the power save circuit makes the main bias current sources stop operating. As a result, the whole circuits are disable. ( The whole circuits mean the driver circuit, the input Op-amp circuit, and the normal Op-amp circuit.) 2. Guaranteed field.(No EDS/Final test)
10
FAN8035
Electrical Characteristics (Continued)
(SVCC = 5V, PVCC1 = 5V, PVCC2 = 12V, TA = 25C, unless otherwise specified) Parameter NORMAL OP AMP CIRCUIT 1 Input Offset Voltage2 Input Bias Current2 High Level Output Voltage2 Low Level Output Voltage2 Output Sink Current2 Output Source Current2 Common Mode Input Open Loop Voltage Range2*note
note
Symbol VOF2 IB2 VOH2 VOL2 ISINK2 ISOU2 Vicm2 GVO2 RR2 CMRR2 SR2 VOF3 IB3 VOH3 VOL3 ISINK3 ISOU3
note
Conditions RL= 50 RL= 50 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p RL = 50 RL = 50 VIN = -75dB VIN = -20dB, f = 120Hz VIN = -20dB Square, Vout = 3Vp-p PVCC2 = 11V, VCTL = 3V, RL= 45 PVCC2 = 13V, VCTL = 4.5V, RL= 45 PVCC2 = 11V, VCTL = 1.5V, RL = 10 VCTL=3V, IL=100mA 400mA VIN = 5V, 5V VIN = 0V, 0V
Min. -10 4.4 2 2 -0.3 -15 3 10 10 2 2.5 -40 -40
Typ. 4.7 0.2 4 4 80 65 80 1.5 3.8 1.0 80 65 80 1.5 6 9 3 300 -
Max. +10 400 0.5 4.0 +15 400 1.5 0.5 3.5 700 +40 +40
Unit mV nA V V mA mA V dB dB dB V/s mV nA V V mA mA dB dB dB V/s V V V V V mV mV mV
Gain2*note
Ripple Rejection Ratio2*
Common Mode Rejection Ratio2*note Slew Rate2*note NORMAL OP AMP CIRCUIT 2 Input Offset Voltage3 Input Bias Current3 High Level Output Voltage3 Low Level Output Voltage3 Output Sink Current3 Output Source Current3 Open Loop Voltage Gain3* Ripple Rejection Common Mode Rejection Ratio3*note Slew Rate3*note TRAY DRIVE CIRTUIT Input High Level Voltage Input Low Level Voltage Output Voltage1 Output Voltage2 Output Voltage3 Output Load Regulation Output Offset Voltage1 Output Offset Voltage2 Ratio3*note
GVO3 RR3 CMRR3 SR3 VIH VIL VO1 VO2 VO3 VRL VOO1 VOO2
Note: Guaranteed field.(No EDS/Final test)
11
FAN8035
Application Information
1. Thermal Shutdown
* The TSD circuit is activated at the junction temperature of 160C and deactivated at 135C with the hysteresis of 25C. During the thermal shutdown, the TSD circuit keeps all the output driver off.
SVCC IREF R1 Q0 R2 Hysteresis Ihys R3 Output driver Bias
2. CH Mute Function
* When the mute pin is high, the TR Q1 is on and Q2 is off, so the bias circuit is enabled. When the mute pin is low (GND), the TR Q1 is off and Q2 is on, so the bias circuit is disabled. * During the mute on state, all the circuit blocks except for the variable regulator remain off, and the low power quiescent state is established. * Truth table is as follows; Pin 19, 20, 21 High Low Mute Mute-Off Mute-On
19 20 21 Q1 SVCC Bias Blocks (5-CH BTL)
Q2
3. Power Save Function
* When the pin39 is high, the TR Q3 becomes on and Q4 off, so the bias circuit is enabled. When the pin39 is low (GND) , the TR Q3 becomes off and Q4 is on, so the bias circuit is disabled. * During the power save on state, this function keeps all the circuit blocks off, and the low power quiescent state is established. * Truth table is as follows; Pin39 High Low Power Save Power Save Off Power Save On
SVCC Main Bias
39 Q3
Q4
4. TDS Monitor Function
* Pin22 is TSD monitor pin, which detects the state of the TSD block and generates the TSD-monitor signal. * In the normal state Q5 is on, and Q6 is off. When the TSD block is activated Q5 becomes off, and thus the voltage of pin22 keeps low. * Truth table is as follows; TSD TSD Off TSD On Pin22 High Low
VCC R(external) SVCC
22 Q6 Q5
20K
12
FAN8035
5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part
40K VREF
43
10K 10K IN+
DO+
28 30 32 35 37
48 1
3 4
6 7
9 10
12 13
Vin INOUT PVCC1(PVCC2) + VDP 60K Vp Vp
40K M 40K 10K 10K 40K DO27 29 31 34 36
2
5
8
11
14
62K
QP
* The Vref at pin 43 is for eliminating the dc components from the input signals and can set by an exteranl circuit. * The voltage gain from Vin to output is as follows ;
Vin = Vref + V DOP = V D + 4 V DON = V D - 4 V Vout = DOP - DON = 8 V Vout Gain = 20 log ------------ = 20 log 8 = 18dB V
* * * *
Where V means just ac component. The total input to output voltage gain is the sum of the input OP amp network gain and 18dB. The output stage is the balanced transformerless (BTL) driver. The bias voltage Vp is expressed as ;
62k V P = ( PVCC1 - V DP - V CESAT Q P ) x ------------------------- + V CESAT Q P 60k + 62k PVCC1 - V DP - V CESAT Q P = ------------------------------------------------------------------------- + V CESAT Q P 1.97
----------
(1)
13
FAN8035
6. Tray, Changer,panel Motor Drive Part
out 1 24
M
out 2 25
D
D
LEVEL SHIFT 6.5V CTL 15 S.W 0 3.25V VCTL M.S.C V(out1,out2)
IN FWD 16
IN REV 17
* Rotational direction control The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as follows; INPUT FWD H H L L REV H L H L OUT 1 Vp H L OUTPUT OUT 2 Vp L H State Brake Forward Reverse Hign impedance
* Where Vp(Power reference voltage) is approximately 3.75V at PVCC2=8V according to equation (1). * Motor speed control (When SVCC=PVCC2=8V) - The maximum torque is obtained when the pin15(CTL) is open. - If the voltage of the pin15 (CTL) is 0V, the motor will not operate. - When the control voltage (pin15) is between 0 and 3.25V, the differential output voltage V(out1,out2) is about two times of control voltage. The output gain is 6dB. - When the control voltage is greater than 3.25V, the output voltage is saturated at the 6.5V because of the output swing limitation.
14
FAN8035
Test Circuits
VCC
1 OP IN (+) OP IN (-) OP OUT
50 OP IN (+) OP OUT OP IN (-)
100F 2 + + 1000F RIPPLE
VREF
2.5V
OP IN (+) OP IN (-) OP OUT IN1- 1
48 IN1+
47 OPIN1+
46 OPIN1-
45 OPOUT1
44 SVCC
43 VREF
42 OPIN2+
41 OPIN2-
40 OPOUT2
39 PS
38 PVCC1
37 DO1+ 36 DO1-
RL1
2 OUT1 3 IN2+
DO2+ 35 DO2- 34
RL2
OP IN (+) OP IN (-) OP OUT
4 IN25 OUT2 6 IN3+
PGND1 33 DO3+ 32 DO3- 31 RL3
OP IN (+) OP IN (-) OP OUT
FAN8035
7 IN3- DO4+ 30 DO4- 29 DO5+ 28 DO5- 27 MUTE12 MUTE34 MUTE5 TSD_M PVCC2 SGND OUT5 DO6- PGND2 26 25 DO6+ RL7 IL IL FWD RL5 RL4 8 OUT3 9 IN4+ 10 IN4- 11 OUT4 IN5+ 12 IN5-
OP IN (+) OP IN (-) OP OUT
OP IN (+) OP IN (-) OP OUT
CTL
13
14
15
16
REV 17
18
19
20
21
22
23
24
CTL
INA
INB
OP-AMP PART
OPIN(+) OPIN(-) OPOUT
A 1 VPULSE 2 VA 3 1
B 2 VB C 1 2 VCC 3 50 D VOUT
15
FAN8035
Typical Application Circuits 1
[Voltage control mode]
SVCC
PVCC1
POWER SAVE FOCUS
48 IN1+ IN1- 1
47 OPIN1+
46 OPIN1-
45 OPOUT1
44 SVCC
43 VREF
42 OPIN2+
41 OPIN2-
40 OPOUT2
39 PS
38 PVCC1
37 DO1+ 36 DO1- TRACKING
2 OUT1 3 IN2+ 4 IN25 OUT2 6 IN3+
DO2+35 DO2- 34
PGND1 33 DO3+ 32 DO3- 31 M SLED
FAN8035
7 IN3- 8 OUT3 9 IN4+ 10 IN4- MUTE12 MUTE34 TSD_M MUTE5 PVCC2 SGND OUT5 11 OUT4 IN5- IN5+ 12 FWD DO4+ 30 DO4- 29 DO5+ 28 DO5-27 PGND2 DO6- 26 25 DO6+ M TRAY M SPINDLE
CTL
REV
13
14
15
16
17
18
19
20
21
22
23
24
pvcc2
PVCC2
SPINDLE MUTE SLED MUTE FOCUS, TRACKING, MUTE
TSD MONITOR VREF FOCUS TRACKING INPUT INPUT SLED INPUT SPINDLE INPUT TRAY TRAY CONTROL INPUT
[SERVO PRE AMP]
[CONTROLLER]
16
FAN8035
Typical Application Circuits 2
[Differential PWM control mode ]
SVCC
PVCC1 POWER SAVE FOCUS
48 IN1+ IN1- 1
47 OPIN1+
46 OPIN1-
45 OPOUT1
44 SVCC
43 VREF
42 OPIN2+
41 OPIN2-
40 OPOUT2
39 PS
38 PVCC1
37 DO1+ 36 35 DO1- TRACKING M SLED M SPINDLE M TRAY
2 OUT1 3 4 5 IN2+ IN2OUT2
DO2+
DO2- 34 PGND1 33 DO3+ 32 DO3- 31
6 IN3+
FAN8035
7 8 9 10 11 IN5+ 12 IN3- OUT3 IN4+ DO4+ 30 DO4- 29 DO5+ 28 DO5-27 MUTE12 MUTE34 MUTE5 TSD_M PVCC2 PGND2 26 DO6- 24 25 DO6+ SGND 18 OUT5
IN4-
OUT4 IN5- 13 FWD 16 CTL REV 17
14
15
19
20
21
22
23
PVCC2
SPINDLE MUTE SLED MUTE FOCUS, TRACKING MUTE
pvcc2
TSD MONITOR VREF FOCUS TRACKING INPUT INPUT SLED INPUT SPINDLE INPUT TRAY TRAY CONTROL INPUT
[SERVO PRE AMP]
[CONTROLLER]
Note: Radiation pin is connected to the internal GND of the package.
17
FAN8035
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/28/03 0.0m 001 Stock#DSxxxxxxxx 2003 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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